1. The Field of the Invention
The present invention relates to methods of making a plug and metallization line structure in microelectronic devices. More particularly, the present invention relates to methods of minimizing resistance in the interface between plugs or contacts and the metallization lines connected to them. The present invention is also particularly drawn to methods of minimizing electromigration due to minimized interface resistance and selected alloying. The present invention is also drawn to improving depth-of-focus restrictions in the process of connecting plugs or contacts to metallization lines.
2. The Relevant Technology
The process of forming contacts in semiconductors and the subsequent wiring of those contacts have several technical obstacles. These obstacles arise during fabrication and may be due to the use of differing materials. Some obstacles include depth-of-focus photolithographic problems, dissimilar metal-metal interface problems, electromigration problems, and irregular or large grain formation problems.
One technical obstacle is depth-of-focus photolithographic requirements in metallization line formation. Formation of metallization lines follows contact plug formation. During contact plug formation, a metallization line used to form the plug may have a non-planar and irregular surface above the contact hole where the plug is to be formed. The non-planarity of the metallization layer is due to the use of a portion of the metallization material that is needed to fill up the contact hole. Non-planarity, and the rough topography of the metallization layer, causes depth of focus problems in subsequent photolithography steps. These problems cause irregular metallization line widths that lead to unpredictable resistances along the metallization lines, as well as unreliable device speeds.
The problem of a rough surface can be ameliorated by reflow methods, but even with reflow, there remains an uneven surface topography.
Another technical obstacle is resistance in metal-to-metal interfaces between plug and metallization line. This obstacle arises when two disparate metals make up the plug and metallization line, respectively, or even when two metals of the same composition are poorly interfaced. The process of forming contacts in semiconductors and the subsequent wiring of those contacts to form a completed integrated circuit conventionally comprises two steps. The first step comprises forming titanium or tungsten plugs that are filled into contact holes by such methods as cold or hot deposition, cold-slow, or hot-fast force filling, or metal reflow into the contact holes, followed by an etchback that leaves only titanium or tungsten plugs isolated in the underlying silicon substrate. The second step comprises forming a metallization line over the plugs.
Electrical conduction at the titanium or tungsten interface with the metallization line can be poor in that a completely connected interface area is difficult to substantially achieve, particularly where dissimilar metals are involved. Because resistance in electrical conduction is a function of cross-sectional area through a conductive body, a less than completely connected interface between plug and metallization line causes a higher resistance than that contemplated by the design geometries of the plug-to-metallization line surface area interface. In addition to incomplete interfacial contact, filling contact holes with titanium or tungsten requires high temperatures and pressures that cause large or irregular grain structures to grow. These large or irregular grain structures resist flow and etchback and do not conduct current as well as fine-grained structures.
Still other technical obstacles are electromigration and metal creep. These involve the transport of metal atoms opposite the direction of electron flow in the lines, and can lead to failure of the lines.
Al—Cu electromigration in a structure with Al—Cu metallization lines and Ti or W plugs is well established. The phenomenon occurs because Cu diffusivity through Ti or W is much lower than through Al. Therefore, the Cu is depleted from the area of the Ti or W plug by the current flow and not replaced, leading to failure at the interface between the Ti or W plug and the Al-Cu metallization lines.
Metal creep, on the other hand, occurs due to the differences in the thermal coefficients of expansion between metals, insulators, and silicon wafers. The differences in thermal coefficients of expansion can build up stress in the metallization lines, which can lead to migration of atoms in the metallization line to the various areas of high stress and strain. This migration of atoms forms voids or vacancies in the metallization line that can cause creep failure. Additional solutions that can control both the electromigration and metal creep problems are desirable.
Yet another technical obstacle involves large or irregular grain growth during the formation of metallization lines. Large or irregular grain growth can be caused by high processing temperatures, a high contact channel density in a dielectric substrate, and the interfaces between disparate metals. For example, where a wetting surface layer is placed upon a substrate to assist in metal flow, interaction between the wetting surface layer and the metallization material can result in large or irregular grain growth.
In the case of a titanium or titanium nitride wetting surface layer, an aluminum metallization layer can react with the wetting surface layer to cause titanium aluminide intermetallic combinations that have large grain cluster formations. Large grain structures adversely affect reflow capabilities and resist planarization. Such adverse effects prevent proper plug filling and the result is poor electrical conductivity and slower and less reliable devices.